# Hire the best remote Physical Design Engineer employees

Discover 32 remote Physical Design Engineer workers who are looking for their next full-time, part-time or freelance opportunity on Himalayas.

Source: https://himalayas.app/talent/physical-design-engineer

## 32 remote workers

| Person | Role | Location | Salary expectations | Intro |
| --- | --- | --- | --- | --- |
| [himanshu gome](https://himalayas.app/@himanshugome) | Physical Design Engineer | India |  | Senior Physical Design Engineer specializing in advanced-node VLSI implementation. |
| [Shagufta Mujeeb](https://himalayas.app/@shaguftamujeeb) | Physical Design Engineer | India |  | VLSI Physical Design Engineer specializing in advanced-node timing closure and PnR automation. |
| [JAHNAVI MUDILI](https://himalayas.app/@jahnavimudili) | Physical Design Engineer | India |  | I'm building VLSI physical design skills through RTL-to-GDSII, synthesis, floorplanning, and timing optimization. |
| [Mohit Patle](https://himalayas.app/@mohitpatle) | Mechanical Design Engineer | India |  | Senior Physical Design Engineer specializing in floorplan integration and reliability verification. |
| [K P Ruchitha](https://himalayas.app/@kpruchitha) | Mechanical Design Engineer | India |  | Dedicated graduate seeking entry-level Physical Design Engineer position. |
| [Sneha Garag](https://himalayas.app/@snehagarag) | Physical Design Engineer | India |  | Entry-level VLSI Physical Design Engineer skilled in RTL-to-GDSII flow. |
| [Keerthi Sree](https://himalayas.app/@keerthisree) | Physical Design Engineer | India |  | VLSI Physical Design Engineer skilled in 28nm PNR flows. |
| [Ashiq Vali](https://himalayas.app/@ashiqvali) | Mechanical Design Engineer | India |  | Aspiring Physical Design Engineer with expertise in VLSI technology. |
| [nikhitha annthomas](https://himalayas.app/@nikhithaannthomas) | Physical Design Engineer | India |  | VLSI Physical Design Engineer delivering RTL-to-GDSII timing, PnR, and power-optimized SoCs. |
| [Gururaj Joshi](https://himalayas.app/@gururajjoshi) | Physical Design Engineer | India |  | Experienced VLSI physical design engineer specializing in RTL2GDS and low-power flows. |
| [Azam Shah](https://himalayas.app/@azamshah) | Physical Design Engineer | India | 140k+ INR | Physical Design Engineer at AMD India who contributed to five 6 nm ASIC tape-outs from netlist to GDSII. |
| [M S](https://himalayas.app/@ms019) | Physical Design Engineer | Japan | 2580k+ JPY | Physical Design Engineer at TSMC implementing advanced-node SoCs at 2 nm and 3 nm. |
| [Pradeep Chowdary Adusumalli](https://himalayas.app/@pradeepchowdaryadusu) | Physical Design Engineer | India |  | Physical Design Engineer skilled in low-power, multi-voltage ASIC implementation. |
| [Abdalah adan](https://himalayas.app/@abdalahadan) | Physical Design Engineer | United States |  | Physical Design Engineer delivering RTL-to-GDS flows and power-aware signoff for advanced-node SoCs. |
| [Vinay kumar Jajerao](https://himalayas.app/@vinaykumarjajerao) | Physical Design Engineer | India | 2451k+ INR | Physical Design Engineer II at Cadence Design System, achieving 99% MFU through floorplan experiments for a TSMC N5 chip project. |
| [Mocharla Mythili](https://himalayas.app/@mocharlamythili) | Physical Design Engineer | India | 140k+ INR | Physical Design Engineer working on Synopsys ICC2 chip design, including floorplanning, CTS, routing, and timing sign-off. |
| [Rishith Varma](https://himalayas.app/@rishithvarma) | Asic Verification Engineer | India |  | ASIC Physical Design engineer skilled in block-level PnR, timing closure, and congestion resolution. |
| [Harshan K](https://himalayas.app/@harshank) | Physical Designer | India |  | VLSI physical design trainee skilled in RTL-to-GDSII flow, timing closure, and Tcl automation. |
| [Robin 11](https://himalayas.app/@robin11) | Physical Design Engineer | India |  | Physical Design Engineer with 7 years’ experience optimizing timing, power, and layout across 2nm–14nm. |
| [Vidyasagar Belkatte](https://himalayas.app/@vidyasagarbelkatte) | Physical Design Engineer | India | 435k+ INR | Aspiring Physical Design Engineer trained in the RTL-to-GDSII flow; worked on a full-chip ASIC design using TSMC 65nm technology. |

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To contact someone, message them from their profile with a Himalayas employer account: [Hire on Himalayas](https://himalayas.app/hire).