# Hire the best remote Design Verification employees

Discover 89 remote Design Verification workers who are looking for their next full-time, part-time or freelance opportunity on Himalayas.

Source: https://himalayas.app/talent/design-verification

## 89 remote workers

| Person | Role | Location | Salary expectations | Intro |
| --- | --- | --- | --- | --- |
| [NagendraReddy User](https://himalayas.app/@nagendrareddyuser1) | Design Verification Engineer | India | 30k+ USD | Design Verification Engineer focused on SystemVerilog and UVM, with an AXI4 verification environment covering all five channels. |
| [Aditya Raut](https://himalayas.app/@adityaraut3) | Design Verification Engineer | India |  | I design and verify FPGA-based digital interfaces and high-speed arithmetic RTL. |
| [Lavanya-G4 Vlsi User](https://himalayas.app/@lavanya-g4vlsiuser) | Verification Engineer | India |  | Aspiring Design Verification Engineer experienced in Verilog, SystemVerilog and RTL verification. |
| [Aishwarya Subramanian](https://himalayas.app/@aishwaryasubramanian) | Senior Verification Engineer | India |  | Skilled design verification engineer focused on optimizing testbench performance. |
| [Vidhi Radhanpura](https://himalayas.app/@vidhiradhanpura) | Verification Engineer | India |  | Verification engineer specializing in VLSI design and UVM-based functional verification with RTL expertise. |
| [Rubeena Tarannum](https://himalayas.app/@rubeenatarannum) | VLSI Engineering | India |  | VLSI design and verification trainee focused on reliable, standards-compliant IC development. |
| [Krishnam Shastri](https://himalayas.app/@krishnamshastri) | Design Verification Engineer | India | 1490k+ INR | Design Verification Engineer at NXP Semiconductors who achieved formal sign-off for multiple RTL blocks across SoCs. |
| [Tehrim k](https://himalayas.app/@tehrimk) | Design Verification Engineer | India | 650k+ INR | I build UVM verification environments for AMBA protocols and RTL designs. |
| [Rajesh Valipi](https://himalayas.app/@rajeshvalipi) | Design Verification Engineer | India |  | I’m a Design Verification Engineer specializing in UVM SystemVerilog protocol and VIP development. |
| [akhil User](https://himalayas.app/@akhiluser4) | Design Verification Engineer | India | 140k+ INR | Design Verification Engineer at Semtech Corporation who verified DMA subsystems and high-speed PCIe and memory interfaces. |
| [Spoorthi Naina Poshala](https://himalayas.app/@spoorthinainaposhala) | Design Verification Engineer | United States | 112k+ USD | Design Verification Engineer at Analog Devices who verified an 800G Ethernet switch fabric across 32 high-speed ports. |
| [Sindhu G](https://himalayas.app/@sindhug1) | Design Verification Engineer | United States | 60k+ USD | Graduate Verification Engineer at Arm executing CPU/SoC regressions and debugging SystemVerilog/UVM verification failures. |
| [Twaheer N](https://himalayas.app/@twaheern) | Design Verification Engineer | India | 140k+ INR | Design Verification Engineer at Saksham Semiconductors who developed RTL for 5+ IP blocks and achieved 98% functional coverage with a UVM testbench. |
| [Akhilesh Ibrahimpet](https://himalayas.app/@akhileshibrahimpet) | Design Verification Engineer | India |  | I build SystemVerilog/UVM verification environments for RTL, memory controllers, and AMBA protocol designs. |
| [RAVINDRA SINGH](https://himalayas.app/@ravindrasingh6) | Design Verification Engineer | Ireland | 90k+ EUR | IP/SoC design verification consultant at Logixchip Technologies, verifying AI compute SoCs and die-to-die interconnects. |
| [Keshava jaya ram Chitturi](https://himalayas.app/@keshavajayaramchittu) | Verification Engineer | India |  | Verification engineer specializing in UVM verification, FPGA validation, and debugging for camera ISP and AI accelerators. |
| [Bala Venkateswara Gupta](https://himalayas.app/@balavenkateswaragupt) | Design Verification Engineer | India | 2500k+ INR | Design Verification Engineer at Soctronics, verifying AMD Audio IP across two SoC programs and validating low-power behavior. |
| [Chirag Dalsaniya](https://himalayas.app/@chiragdalsaniya) | Asic Verification Engineer | India | 1058k+ INR | I build and verify RTL designs using Verilog, SystemVerilog, UVM, and coverage-driven verification. |
| [Nithu User](https://himalayas.app/@nithuuser) | Verification Engineer | India |  | Electronics/ECE graduate specializing in SystemVerilog UVM functional verification. |
| [Faisal Saeed Awan](https://himalayas.app/@faisalsaeedawan) | Verification Engineer | Pakistan |  | I’m a UVM ASIC/SoC Functional Verification Engineer focused on first-pass silicon. |

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To contact someone, message them from their profile with a Himalayas employer account: [Hire on Himalayas](https://himalayas.app/hire).