# Hire the best remote Asic Verification Engineer employees

Discover 83 remote Asic Verification Engineer workers who are looking for their next full-time, part-time or freelance opportunity on Himalayas.

Source: https://himalayas.app/talent/asic-verification-engineer

## 83 remote workers

| Person | Role | Location | Salary expectations | Intro |
| --- | --- | --- | --- | --- |
| [Nitu Kumari](https://himalayas.app/@nitukumari) | Senior Verification Engineer | India |  | Experienced ASIC Verification Engineer specializing in pre-silicon validation. |
| [Chirag Dalsaniya](https://himalayas.app/@chiragdalsaniya) | Asic Verification Engineer | India | 1058k+ INR | I build and verify RTL designs using Verilog, SystemVerilog, UVM, and coverage-driven verification. |
| [Ganesh Gorli](https://himalayas.app/@ganeshgorli) | Asic Verification Engineer | United States |  | I build and verify FPGA and ASIC systems for AI computing. |
| [Faisal Saeed Awan](https://himalayas.app/@faisalsaeedawan) | Verification Engineer | Pakistan |  | I’m a UVM ASIC/SoC Functional Verification Engineer focused on first-pass silicon. |
| [Andrew Chen](https://himalayas.app/@andrewchen4) | Fpga Engineer | United States |  | Senior FPGA/ASIC verification engineer specializing in UVM, constrained-random, coverage-driven closure, and high-speed protocol validation. |
| [Pragati Piragannavar](https://himalayas.app/@pragatipiragannavar) | ASIC and SoC Design Engineer | India | 6949k+ INR | ASIC and SoC design verification engineer who verified an AXI4-Lite slave and built RTL projects including a RISC-V RV32I processor. |
| [Rishith Varma](https://himalayas.app/@rishithvarma) | Asic Verification Engineer | India |  | ASIC Physical Design engineer skilled in block-level PnR, timing closure, and congestion resolution. |
| [Ram kumar User](https://himalayas.app/@ramkumaruser2) | Asic Verification Engineer | India | 1118k+ INR | Aspiring ASIC Design Verification engineer with SPI and Router 1x3 verification projects using SystemVerilog testbenches and assertions. |
| [Akhilesh Ibrahimpet](https://himalayas.app/@akhileshibrahimpet) | Design Verification Engineer | India |  | I build SystemVerilog/UVM verification environments for RTL, memory controllers, and AMBA protocol designs. |
| [PRANUTHI POLIPOGU](https://himalayas.app/@pranuthipolipogu) | ASIC FPGA Engineer | India | 70k+ INR | ASIC/FPGA Design Engineer who developed an AXI-to-AHB bridge and reusable UVM testbench for protocol verification. |
| [Astitva Sharma](https://himalayas.app/@astitvasharma) | VLSI Design Intern | India |  | VLSI engineer specializing in RTL design, verification, and FPGA/ASIC flows. |
| [Tehrim k](https://himalayas.app/@tehrimk) | Design Verification Engineer | India | 650k+ INR | I build UVM verification environments for AMBA protocols and RTL designs. |
| [Nithu User](https://himalayas.app/@nithuuser) | Verification Engineer | India |  | Electronics/ECE graduate specializing in SystemVerilog UVM functional verification. |
| [Keshava jaya ram Chitturi](https://himalayas.app/@keshavajayaramchittu) | Verification Engineer | India |  | Verification engineer specializing in UVM verification, FPGA validation, and debugging for camera ISP and AI accelerators. |
| [HARI MADDUKURI](https://himalayas.app/@harimaddukuri) | RTL Design Engineer | India | 70k-150k USD | I build RTL and FPGA solutions for radar, timing, and hardware validation. |
| [Korrapolu Eswar Adithya](https://himalayas.app/@korrapolueswaradithy) | Design Verification Engineer | India |  | I’m an aspiring VLSI RTL design and verification engineer building ASIC/FPGA-ready modules, testbenches, and SVA-driven validation. |
| [Richard Sánchez M](https://himalayas.app/@smrichdef) | Electronics Engineer | Costa Rica |  | Electronics engineer specializing in hardware, verification, and PCB design. |
| [veda s](https://himalayas.app/@vedas) | ASIC Design Engineer | India |  | RTL/ASIC Design Engineer specializing in RTL quality, CDC sign-off, and SoC integration. |
| [Srikanta S M](https://himalayas.app/@srikantasm) | Design Verification Engineer | India | 300k+ INR | Staff Verification Engineer at Krutrim verifying IEEE 754 floating-point IP for an AI accelerator chiplet using SystemVerilog and UVM. |
| [Asaf Zini](https://himalayas.app/@asafzini) | Digital Design Engineer | Israel | 220k+ ILS | I build RTL-to-GDS ASICs and FPGA systems, with hands-on digital verification and timing closure experience. |

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