# Hire the best remote ASIC FPGA Engineer employees

Discover 87 remote ASIC FPGA Engineer workers who are looking for their next full-time, part-time or freelance opportunity on Himalayas.

Source: https://himalayas.app/talent/asic-fpga-engineer

## 87 remote workers

| Person | Role | Location | Salary expectations | Intro |
| --- | --- | --- | --- | --- |
| [Craig Noble](https://himalayas.app/@craignoble) | Electronics Engineer | United Kingdom | 75k-85k GBP | I design digital hardware and FPGA solutions for telecommunications and aviation products. |
| [Ganesh Gorli](https://himalayas.app/@ganeshgorli) | Asic Verification Engineer | United States |  | I build and verify FPGA and ASIC systems for AI computing. |
| [Eric Hamel](https://himalayas.app/@erichamel) | Fpga Engineer | Canada | 149k+ CAD | I build and verify FPGA, ASIC, and high-speed hardware for radios, aerospace, networking, and test systems. |
| [Andrew Chen](https://himalayas.app/@andrewchen4) | Fpga Engineer | United States |  | Senior FPGA/ASIC verification engineer specializing in UVM, constrained-random, coverage-driven closure, and high-speed protocol validation. |
| [PRANUTHI POLIPOGU](https://himalayas.app/@pranuthipolipogu) | ASIC FPGA Engineer | India | 70k+ INR | ASIC/FPGA Design Engineer who developed an AXI-to-AHB bridge and reusable UVM testbench for protocol verification. |
| [HARI MADDUKURI](https://himalayas.app/@harimaddukuri) | RTL Design Engineer | India | 70k-150k USD | I build RTL and FPGA solutions for radar, timing, and hardware validation. |
| [yh l](https://himalayas.app/@yhl) | Fpga Engineer | China |  | I build production FPGA and embedded systems for high-speed communications and satellite equipment. |
| [Joshua Benjamin](https://himalayas.app/@joshuabenjamin) | ASIC FPGA Design and Verification Intern | Nigeria | 60k+ USD | ASIC/FPGA design intern at ChipMango who delivered an AES-128/SHA-256 coprocessor running on FPGA hardware. |
| [Asaf Zini](https://himalayas.app/@asafzini) | Digital Design Engineer | Israel | 220k+ ILS | I build RTL-to-GDS ASICs and FPGA systems, with hands-on digital verification and timing closure experience. |
| [KANAN BAJAJ](https://himalayas.app/@kananbajaj1) | RTL Design Engineer | India |  | I build RTL, ASIC, and FPGA systems from Verilog design through implementation. |
| [Aravind Pulugundla](https://himalayas.app/@aravindpulugundla) | ASIC Validation Architect | United States | 200k+ USD | Sr. Principal Architect Engineer at Palo Alto Networks, leading validation of NGFW Gen4–Gen6 SoCs and identifying four critical RTL defects. |
| [a varma](https://himalayas.app/@avarma) | ASIC FPGA Engineer | United States |  | ASIC/FPGA verification engineer at Twinwing Labs, building a NASDAQ tick-to-trade FPGA system. |
| [Manar Tarek](https://himalayas.app/@manartarek) | Ic Design Engineer | Egypt | 30k+ USD | I build and verify Verilog RTL for FPGA and ASIC-oriented digital IC designs. |
| [SAPTAK MAITY](https://himalayas.app/@saptakmaity) | VLSI Engineer | India | 70k+ INR | VLSI Design Engineer working on an FPGA FFT denoising accelerator, with RTL-to-GDS and low-power ASIC design experience. |
| [sreeraj kaipurath](https://himalayas.app/@sreerajk) | Fpga Engineer | India |  | Final-year Electrical & Electronics student with hands-on VLSI, industrial automation, and embedded systems experience. |
| [Ripudaman Khattar](https://himalayas.app/@ripudamankhattar) | Embedded Systems Engineer | Sweden |  | Embedded engineer specializing in ASIC/FPGA verification and embedded Linux development, eager to build reliable hardware systems. |
| [ISMAIL HAJJY](https://himalayas.app/@ismailhajjy) | ASIC Design Engineer | Morocco | 58k+ USD | I build low-power ASIC, FPGA, and embedded systems from RTL through verification. |
| [皓 李](https://himalayas.app/@0001895) | Fpga Engineer | China |  | FPGA与数字IC开发工程师，专注Zynq SoC系统与高速数据处理。 |
| [Prateeksha Hiremath](https://himalayas.app/@prateekshahiremath) | Fpga Engineer | India |  | M.Tech candidate in VLSI & Nanotech specializing in FPGA and embedded systems. |
| [Astitva Sharma](https://himalayas.app/@astitvasharma) | VLSI Design Intern | India |  | VLSI engineer specializing in RTL design, verification, and FPGA/ASIC flows. |

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