# Hire the best remote ASIC Engineer employees

Discover 99 remote ASIC Engineer workers who are looking for their next full-time, part-time or freelance opportunity on Himalayas.

Source: https://himalayas.app/talent/asic-engineer

## 99 remote workers

| Person | Role | Location | Salary expectations | Intro |
| --- | --- | --- | --- | --- |
| [Rishith Varma](https://himalayas.app/@rishithvarma) | Asic Verification Engineer | India |  | ASIC Physical Design engineer skilled in block-level PnR, timing closure, and congestion resolution. |
| [Pragati Piragannavar](https://himalayas.app/@pragatipiragannavar) | ASIC and SoC Design Engineer | India | 6949k+ INR | ASIC and SoC design verification engineer who verified an AXI4-Lite slave and built RTL projects including a RISC-V RV32I processor. |
| [Chirag Dalsaniya](https://himalayas.app/@chiragdalsaniya) | Asic Verification Engineer | India | 1058k+ INR | I build and verify RTL designs using Verilog, SystemVerilog, UVM, and coverage-driven verification. |
| [vaibhav vaidya](https://himalayas.app/@vaibhavvaidya1) | ASIC Design Engineer | India | 5005k+ INR | Senior ASIC Design Engineer at NVIDIA who designed USB debug protocol RTL and led USB controller silicon bringup. |
| [Nitu Kumari](https://himalayas.app/@nitukumari) | Senior Verification Engineer | India |  | Experienced ASIC Verification Engineer specializing in pre-silicon validation. |
| [Ganesh Gorli](https://himalayas.app/@ganeshgorli) | Asic Verification Engineer | United States |  | I build and verify FPGA and ASIC systems for AI computing. |
| [Zain Saeed](https://himalayas.app/@zainsaeed1) | ASIC Design Engineer | Pakistan |  | I build RTL-to-GDSII processors and ASIC implementations for RISC-V and data-intensive hardware systems. |
| [Khushal Patil User](https://himalayas.app/@khushalpatiluser) | ASIC Physical Design Engineer | India | 608k+ INR | ASIC physical design engineer trained at RV-SKILLS Center For Emerging Technologies; completed a 40nm block-level implementation with DRC-clean routing. |
| [Aravind Pulugundla](https://himalayas.app/@aravindpulugundla) | ASIC Validation Architect | United States | 200k+ USD | Sr. Principal Architect Engineer at Palo Alto Networks, leading validation of NGFW Gen4–Gen6 SoCs and identifying four critical RTL defects. |
| [KANAN BAJAJ](https://himalayas.app/@kananbajaj1) | RTL Design Engineer | India |  | I build RTL, ASIC, and FPGA systems from Verilog design through implementation. |
| [Joao Cassiano](https://himalayas.app/@joaocassiano) | ASIC Design Engineer | Portugal | 35k+ EUR | ASIC Digital Design Sr Engineer at Synopsys, working on digital design after developing RISC-V encryption on FPGA. |
| [Chinmayi M](https://himalayas.app/@chinmayim) | ASIC Design Engineer | India | 1191k+ INR | I build neuromorphic mixed-signal ASICs, from IC layout and verification through tape-out and post-layout validation. |
| [Pradeep Chowdary Adusumalli](https://himalayas.app/@pradeepchowdaryadusu) | Physical Design Engineer | India |  | Physical Design Engineer skilled in low-power, multi-voltage ASIC implementation. |
| [20 Janhavi Saraf](https://himalayas.app/@20janhavisaraf) | Digital Design Engineer | India | 70k+ INR | I design Verilog-based digital ICs, processors, ASIC flows, and embedded hardware systems. |
| [Rozet Khacheryan](https://himalayas.app/@rozetkhacheryan) | ASIC Design Engineer | Armenia | 60k+ USD | STA/Analog Design Engineer who generated timing libraries for analog blocks and resolved timing-path issues. |
| [Deekshith K M](https://himalayas.app/@deekshithkm1) | Embedded Systems Engineer | India |  | I build embedded, IoT, and RISC-V hardware systems for reliable real-time applications. |
| [Faisal Saeed Awan](https://himalayas.app/@faisalsaeedawan) | Verification Engineer | Pakistan |  | I’m a UVM ASIC/SoC Functional Verification Engineer focused on first-pass silicon. |
| [PRANUTHI POLIPOGU](https://himalayas.app/@pranuthipolipogu) | ASIC FPGA Engineer | India | 70k+ INR | ASIC/FPGA Design Engineer who developed an AXI-to-AHB bridge and reusable UVM testbench for protocol verification. |
| [Joshua Benjamin](https://himalayas.app/@joshuabenjamin) | ASIC FPGA Design and Verification Intern | Nigeria | 60k+ USD | ASIC/FPGA design intern at ChipMango who delivered an AES-128/SHA-256 coprocessor running on FPGA hardware. |
| [Asaf Zini](https://himalayas.app/@asafzini) | Digital Design Engineer | Israel | 220k+ ILS | I build RTL-to-GDS ASICs and FPGA systems, with hands-on digital verification and timing closure experience. |

Page 1 of 5. Next page: [page 2](https://himalayas.app/talent/asic-engineer.md?page=2)

To contact someone, message them from their profile with a Himalayas employer account: [Hire on Himalayas](https://himalayas.app/hire).