# Sergej Mutas

Sergej Mutas is a remote worker on Himalayas, Senior Project Manager and Chip Designer at Infineon, based in Germany.

Source: https://himalayas.app/@sergejmutas

```text
Chip designer and project leader at Infineon, developing next-generation IGBTs, Si diodes and SiC MOSFETs for renewable energy applications.
```

| Detail | Value |
| --- | --- |
| Availability | Looking for a job |
| Location | Germany |
| Authorized to work in | Germany |
| Salary expectations | 100k+ EUR |
| Job categories | Hardware Engineer, Project Manager, Hardware Development, Failure Analysis Engineer, Technical Manager |
| Skills | Chip Design, IGBTs, MOSFET, Diodes, Semiconductor Processing, Semiconductor Development, ASICS, Hardware Development, Failure Analysis, APT, TCAD, Project Management, IPMA Level C, III V Fabrication, LED |
| LinkedIn | https://linkedin.com/in/sergejmutas |

## What I'm looking for

```text
I'm seeking a role in hardware development where I can work independently on complex projects.
```

## About

```text
At Infineon, I lead projects and design chips for next-generation IGBTs, alongside work on SiC MOSFETs and Si diodes for renewable energy applications. I hold IPMA Level C certification.

At Bosch, I supported the technology and release of automotive semiconductor ASIC products with internal and external fabs. Before that, at Apple Inc., I helped resolve manufacturing issues for VCSELs on iPhone X, enabling timely production at high yield and a successful product release.

At Apple Inc., I also worked on µLED, OLED, and VCSEL technologies. I planned and executed III-V fabrication processing and contributed to work that helped bring µLED closer to mass production.

Earlier, at Intel, I used TCAD and analytical techniques to debug chip design failures and support front-end and back-end technology development. At AMD/Globalfoundries, I led the spacer module and co-authored two patents on spacer manufacturing and characterization.
```

## Experience

### Senior Project Manager and Chip Designer (current)

[Infineon](https://himalayas.app/companies/infineon-technologies-ag). Sep 2023 - Present

```text
Project leader and chip designer for development of next-gen IGBTs, SiC MOSFETs, and Si diodes for renewable energy applications. Holds IPMA Level C certification.
```

Skills: IGBTs, SiC-MOSFET, Si-Diodes, Project-Management, Chip-Design, IPMA-Level-C

### Technical Manager for ASICs

[Bosch](https://himalayas.app/companies/bosch-group). Aug 2022 - Sep 2023

```text
Provided technological support and release of automotive semiconductor products with internal and external fabs.
```

Skills: ASIC, Automotive-Semiconductors, Technology-Support, Fabrication-Management

### Senior Hardware and Analysis Engineer

[Apple Inc.](https://himalayas.app/companies/apple). Aug 2016 - Jul 2022

```text
Technical project leader for atom probe tomography, responsible for training lab personnel and developing measurement procedures. Key figure between manufacturing, processing, integration, and analysis lab. Involved in III-V fabrication processing and taskforce for novel µLED structures. Helped solve major manufacturing issues for VCSELs on iPhone X, enabling high-yield production and successful p
```

Skills: Atom-Probe-Tomography, III-V-Fabrication, LED, OLEDs, VCSEL, Manufacturing, Analysis, Training, Project-Leadership

### Senior Failure Analysis Engineer

[Intel](https://himalayas.app/companies/intel-corporation). Oct 2012 - Aug 2016

```text
Technical expert for atom probe tomography, responsible for training lab personnel and developing measurement procedures. Used TCAD to debug chip design failures and verify improvements. Involved in front-end and back-end technology development for 10 and 14 nm nodes.
```

Skills: Atom-Probe-Tomography, TCAD, Failure-Analysis, SiGe, SIC, NiSi, CoSi, TiSi, III-V, 10nm, 14nm, Back-End-Of-Line

### Senior Engineer, Technology and Development

[AMD/Globalfoundries](https://himalayas.app/companies/globalfoundries-com). Mar 2011 - Sep 2012

```text
Module leader in the spacer module for 28 and 32 nm technology. Used TCAD to decide chip design and verify manufacturability. Led collaboration between deposition, etch, and electrical characterization teams. Co-author of 2 patents for spacer manufacturing and characterization.
```

Skills: Spacer-Module, 28nm-Technology, 32nm-Design, TCAD, Depositions, Etch, Electrical-Characterization, Patents

## Education

### Technical University Berlin

Ph.D. (Doktor der Ingenieurwissenschaften, Dr.-Ing.), Nanostrukturtechnik

```text
Ph.D. (Dr.-Ing.) under Prof. Dr. John Banhart, focusing on analysis of high-k materials and metal gates for 28 and 32 nm technology nodes.
```

### Julius-Maximilians-Universität Würzburg

Diploma (M.A.) (Diplom Ingenieur Universität), Nanostrukturtechnik

```text
Diploma (M.A.) in Nanostrukturtechnik under Prof. Dr. A. Forchel, including a collaboration with IBM Almaden Research Center.
```

## Tech stack

- LabVIEW

To contact Sergej, message them from this profile with a Himalayas employer account: [Hire on Himalayas](https://himalayas.app/hire).

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