# Puneeth C

Puneeth C is a remote worker on Himalayas, Research and Development Intern at Nokia, based in India.

Source: https://himalayas.app/@puneethc

```text
R&D intern at Nokia who automated Vivado FPGA design flows for 5G PHY layer RU processing.
```

| Detail | Value |
| --- | --- |
| Availability | Looking for a job |
| Location | India |
| Authorized to work in | India |
| Salary expectations | 594k+ INR |
| Job categories | FPGA Design Engineer, RTL Design Engineer, Verification Engineer |
| Skills | FPGA Design, RTL Verification, FPGA Flow, Tcl, Verilog, SystemVerilog, UVM Methodology, 5G PHY, IP Verification, regression analysis, Coverage Analysis, Spiking Neural Networks, Leaky Integrate and Fire Model, Wireless Network on Chip, Congestion Prediction |
| LinkedIn | https://linkedin.com/in/puneeth-c-800442259 |

## About

```text
At Nokia, I automated FPGA design flows for 5G PHY layer RU processing on Xilinx Zynq SoC, using TCL and Vivado to automate RTL synthesis, implementation, and bitstream generation. I also performed IP verification and regression analysis for PHY layer IP blocks.

On my Wireless NOC congestion prediction project, I implemented a Spiking Neural Network and trained a classifier that achieved over 90% congestion prediction accuracy. I’ve also worked on I2C protocol implementation and ANN deployment on FPGA.
```

## Experience

### Research and Development Intern

[Nokia](https://himalayas.app/companies/nokia). Aug 2025 - Jun 2026

```text
Automated FPGA design flows using TCL scripting on Xilinx Zynq SoC for 5G PHY layer RU processing. Performed RTL verification, IP verification, and regression analysis for PHY layer IP blocks.
```

Skills: Tcl, Xilinx-Vivado, Intel-Quartus, Synopsys-Verdi, Genus, Linux, FPGA, RTL-Verification, SystemVerilog, UVM-Methodology

## Education

### The National Institute of Engineering

Bachelor of Engineering, Electronics and Communication. Grade: 8.3/10

Activities and societies: Related Coursework: Analog Electronics, Digital Electronics, Signals and Systems, Control Systems, Communication Systems, DSP, Wireless Communication, VLSI, Computer Networks, C++ OOP, Data Structures

```text
Pursuing a Bachelor of Engineering in Electronics and Communication with an expected graduation in July 2026. Achieved a GPA of 8.3/10.
```

## Tech stack

- GitHub
- Jira
- Python
- C++
- C
- Linux
- Git

To contact Puneeth, message them from this profile with a Himalayas employer account: [Hire on Himalayas](https://himalayas.app/hire).

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