# Pruthvi Gowda M N

Pruthvi Gowda M N is a remote worker on Himalayas, Physical Design Trainee at VloldiFirst Technologies, based in India.

Source: https://himalayas.app/@pruthvigowdamn

```text
Aspiring Physical Design Engineer trained in the RTL-to-GDSII flow, with projects implementing ORCA_TOP and a Cortex-M23 processor.
```

| Detail | Value |
| --- | --- |
| Availability | Looking for a job |
| Location | India |
| Authorized to work in | India |
| Salary expectations | 1025k+ INR |
| Job categories | Physical Design Engineer |
| Skills | ASIC Physical Design, RTL To GDSII, Floor Planning, Placements, Clock Tree Synthesis (CTS), Routing, Static Timing Analysis, Physical Verification, Design Rule Check (DRC), Layout Versus Schematic (LVS), I O, Power Planning, Power Distribution Design, Timing Constraints (SDC), Congestion |
| LinkedIn | https://linkedin.com/in/pruthvi-gowda-m-n-b44660314 |

## What I'm looking for

```text
I'm seeking an entry-level opportunity in the semiconductor industry where I can apply my technical knowledge, gain hands-on experience, and contribute to efficient VLSI design implementation.
```

## About

```text
During my Physical Design Training at VLoldIeFirstTelchechlogiegierivrieaLtiLitedi|Be|Bgenlurluru, I gained hands-on experience with Synopsys IC Compiler (ICC2) and the RTL-to-GDSII flow. I worked on floor planning, placement, CTS, routing, and physical verification.

On the ORCA_TOP project, I performed placement optimization, worked on I/O placement and PDN design, and executed detailed routing and DRC. I also worked on physical design implementation for a Cortex-M23 processor, including timing optimization, DRC and LVS checks, and debugging routing-related violations.
```

## Experience

### Physical Design Trainee

VloldiFirst Technologies

```text
Completed a 6-month training program covering the ASIC RTL-to-GDSII flow, including floor planning, placement, clock tree synthesis, routing, and static timing analysis. Gained hands-on experience with Synopsys IC Compiler (ICC2) for block-level physical design implementation.
```

Skills: RTL-To-GDSII, Floor-Planning, Placements, Clock-Tree-Synthesis, Routing, Static-Timing-Analysis, Physical-Verification, DRC, LVS, Synopsys-ICC2

## Education

### Cauvery Institute of Technology, Mandya

B.E., Electronics and Communication Engineering. Grade: 7.2 CGPA

```text
Pursuing B.E. in Electronics and Communication Engineering with a CGPA of 7.2.
```

### Government PU College

Pre-University, Pre-University Education. Grade: 63.3%

```text
Completed Pre-University Education with a percentage of 63.3.
```

### Morarji Desai Residential School

SSC, Secondary School Certificate. Grade: 86.6%

```text
Completed Secondary School Certificate (SSC) with a percentage of 86.6.
```

## Tech stack

- Linux
- Windows

To contact Pruthvi, message them from this profile with a Himalayas employer account: [Hire on Himalayas](https://himalayas.app/hire).

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