# Pragati Piragannavar

Pragati Piragannavar is a remote worker on Himalayas, Project Intern at Igeek Technologies, based in India.

Source: https://himalayas.app/@pragatipiragannavar

```text
ASIC and SoC design verification engineer who verified an AXI4-Lite slave and built RTL projects including a RISC-V RV32I processor.
```

| Detail | Value |
| --- | --- |
| Availability | Open to opportunities |
| Location | India |
| Authorized to work in | India |
| Salary expectations | 6949k+ INR |
| Job categories | ASIC and SoC Design Engineer, ASIC Design Engineer, SoC Design Engineer |
| Skills | ASIC Design, SoC Design, RTL Design, Design Verification, SystemVerilog, UVM Methodology, Verilog, SVA, AXI, AXI4 Lite, APB, UART, SPI, I2C, AHB |
| LinkedIn | https://linkedin.com/in/pragati-piragannavar |

## What I'm looking for

```text
I’m looking to join a dynamic team of professionals as an ASIC and SoC Design Engineer, where I can share my expertise and contribute to the organization’s success.
```

## About

```text
At Igeek Technologies, I developed and verified an AXI4-Lite slave module with 256x32-bit internal memory, read/write operations, AXI handshake logic, and address decoding. I used a custom SystemVerilog testbench with protocol-compliant stimulus and coverage analysis.

My projects include RTL design and verification for a RISC-V RV32I processor, a full-duplex UART system, an AXI4-Lite-to-APB bridge, and a configurable 1x3 router. I’m pursuing a Post Graduate Program in VLSI ASIC RTL / SoC Design and Verification at M S Ramaiah Institute of Technology.
```

## Experience

### Project Intern

Igeek Technologies. Sep 2023 - Oct 2023

```text
Developed an AXI4-Lite slave interface with RTL design and verification using Verilog and SystemVerilog. Implemented AXI handshake logic, address decoding, and verified with a custom testbench and coverage analysis.
```

Skills: Verilog, SystemVerilog, AXI4-Lite, QuestaSim, RTL-Design, Verification, Coverage-Analysis

## Education

### M S Ramaiah Institute of Technology

Post Graduate Program, VLSI ASIC RTL / SoC Design and Verification

```text
Pursuing a Post Graduate Program in VLSI ASIC RTL / SoC Design and Verification.
```

### M S Ramaiah Institute of Technology

Bachelor of Engineering, Electronics and Instrumentation Engineering

```text
Bachelor of Engineering in Electronics and Instrumentation Engineering, completed in 2025.
```

### Maratha Mandal Polytechnic

Diploma, Electronics and Communication Engineering

```text
Diploma in Electronics and Communication Engineering, completed in 2022.
```

## Tech stack

- Python
- Perl
- C++
- Linux
- Verilog

To contact Pragati, message them from this profile with a Himalayas employer account: [Hire on Himalayas](https://himalayas.app/hire).

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