# ali mehrabadi

ali mehrabadi is a remote worker on Himalayas, Freelance FPGA RTL Design Engineer at Freelance, based in Iran.

Source: https://himalayas.app/@alimehrabadi

```text
FPGA/RTL Design Engineer at Freelance FPGA translating MATLAB signal-processing algorithms into real-time VHDL hardware.
```

| Detail | Value |
| --- | --- |
| Availability | Looking for a job |
| Location | Iran |
| Authorized to work in | Iran |
| Salary expectations | 30k+ USD |
| Job categories | Hardware Engineer, Hardware Engineer, Fpga Engineer, Signal Processing Engineer |
| Skills | RTL Design (VHDL SystemVerilog), Matlab, MicroBlaze, Xilinx Zynq SoCs, VHDL, RTL Design, FPGA Design, Digital Signal Processing, FIR, Digital Filtering, Beamforming, Matrix Inversion, Covariance Matrix Processing, Eigenvalue Decomposition, Pulse Detection, Envelope Detection, Modulation Detection, Feature Extraction |

## What I'm looking for

```text
I'm focused on expanding my expertise in RTL design and ASIC development.
```

## About

```text
I am an FPGA/RTL and Digital Signal Processing Engineer with three years of experience in digital design, real-time signal processing, and high-speed data acquisition. My main strengths are VHDL, AMD/Xilinx Vivado, and translating MATLAB algorithms into efficient, synthesizable hardware. I enjoy taking a design from algorithm modeling through RTL development, simulation, FPGA implementation, and hardware validation.

My career includes engineering roles at Hamgam Radin and Farazaman Afaq Iranian, alongside freelance FPGA work since 2023. I have implemented signal-processing algorithms, developed real-time processing pipelines, and worked on peripheral bring-up using MicroBlaze and Zynq devices. My work involves balancing numerical accuracy, throughput, latency, timing constraints, and FPGA resource utilization.

My project experience includes matrix inversion, covariance matrix computation, beamforming, eigenvalue decomposition, monobit receivers, pulse descriptor word processing, and CDIF-based signal analysis. I have also implemented FIR filters, envelope detection, pulse detection, modulation detection, and signal feature extraction. These projects have strengthened my ability to convert complex mathematical algorithms into practical hardware architectures and verify their behavior against MATLAB models.

My technical achievements include implementing and bringing up 1-Gigabit Ethernet communication over SGMII, developing processing pipelines for high-speed ADC data, and using multi-sample-per-clock architectures for real-time processing. I have optimized RTL designs for timing, resource usage, throughput, and latency, with hands-on experience in pipelining, finite-state machines, clock domain crossing, testbench development, and hardware debugging.

I hold an M.Sc. in Electrical Engineering with a focus on Integrated Circuits from Tarbiat Modarres University, where my thesis involved the design and analysis of a phase-locked loop. I also hold a B.Sc. in Electrical Engineering–Electronics from the University of Mazandaran. This background gives me a foundation in digital systems, CMOS design, and analog and mixed-signal concepts.

I am particularly interested in FPGA acceleration, DSP hardware, high-speed interfaces, and embedded systems built around Zynq and MicroBlaze. I am also expanding my expertise in ASIC development and RTL verification. I am seeking remote engineering roles or freelance projects where I can contribute to challenging FPGA/RTL designs, solve practical implementation problems, and continue developing my technical skills.
```

## Experience

### Freelance FPGA RTL Design Engineer (current)

Freelance. Jan 2023 - Present

```text
Designed and implemented advanced signal processing algorithms on FPGA using VHDL, including matrix inversion, beamforming, and eigenvalue decomposition. Translated MATLAB-based algorithms into synthesizable RTL and developed high-speed data processing pipelines.
```

Skills: VHDL, RTL-Design, FPGA, Matlab, FIR, Envelope-Detection, Pulse-Detection, Signal-Processing, SGMII, Ethernet, ADC-Interfacing, Vivado

## Education

### Tarbiat Modarres University

Master of Science, Electrical Engineering. 2020 - 2023

```text
M.Sc. in Electrical Engineering with a focus on Integrated Circuits. Thesis on the design and analysis of a Phase-Locked Loop (PLL).
```

### University of Mazandaran

Bachelor of Science, Electrical Engineering. 2015 - 2019

```text
B.Sc. in Electrical Engineering with a focus on Electronics. Relevant coursework included digital logic design, digital systems, microprocessors, electronic circuits, and signals and systems.
```

## Tech stack

- MATLAB

To contact ali, message them from this profile with a Himalayas employer account: [Hire on Himalayas](https://himalayas.app/hire).

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